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1 for more information www.linear.com/ltc3624 typical a pplica t ion fea t ures descrip t ion 17v, 2a synchronous step-down regulator with 3.5a quiescent current the lt c ? 3624/LTC3624-2 is a high efficiency 17v, 2a synchronous monolithic step-down regulator. the switch - ing frequency is fixed to 1mhz (ltc3624) or 2.25mhz ( ltc3624 -2) with a 40% synchronization range. the regulator features ultralow quiescent current and high efficiency over a wide v out range. the step-down regulator operates from an input voltage range of 2.7v to 17v and provides an adjustable output range from 0.6v to v in while delivering up to 2a of output current. a user-selectable mode input is provided to allow the user to trade off ripple noise for light load efficiency; burst mode operation provides the highest efficiency at light loads, while pulse-skipping mode provides the lowest voltage ripple. the mode pin can also be used to sync the switching frequency to an external clock. efficiency and power loss vs load 5v v out with 800ma burst clamp, f sw = 1mhz a pplica t ions n wide v in range: 2.7v to 17v n wide v out range: 0.6v to v in n 95% max efficiency n low i q : 3.5a, zero-current shutdown n constant frequency (1mhz/2.25mhz) n fixed v out options available n low dropout operation (100% duty cycle) with ultralow i q n 2a rated output current n 1% output voltage accuracy n current mode operation for excellent line and load transient response n synchronizable to external clock n pulse-skipping, forced continuous, burst mode ? operation n internal compensation and soft-start n overtemperature protection n compact 8-lead dfn (3mm 3mm) package n battery powered equipment n portable instrumentation n emergency radios n general purpose step-down supplies l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6498466, 6611131, 6177787, 5705919, 5847554, 6703692. ltc3624/LTC3624-2 options part name frequency v out ltc3624 1mhz adjustable ltc3624-3.3 1mhz 3.3v ltc3624-5 1mhz 5v LTC3624-2 2.25mhz adjustable LTC3624-23.3 2.25mhz 3.3v LTC3624-25 2.25mhz 5v load current (a) 0 0 efficiency (%) power loss (w) 10 30 40 50 100 70 0.5 1 3624 ta01b 20 80 90 60 0 0.2 0.4 0.6 1.2 1.0 0.8 1.5 2 v out = 5v burst mode operation v in = 12v v in = 8v v in = 6v freq = 1mhz 2.2f 47f 36242 ta01a 3.3h v out 5v 2a v in run sw v in 5.6v to 17v ltc3624-5 gnd fb mode/sync intv cc 10f ltc3624/LTC3624-2 36242fd
2 for more information www.linear.com/ltc3624 a bsolu t e maxi m u m r a t ings v in voltage ................................................. C 0. 3v to 17v run voltage ............................................... C 0.3v to 17v mode/sync, fb voltages ............................ C 0. 3v to 6v intv cc , pgood voltages ............................ C 0.3 v to 6v (note 1) top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 9 gnd 4 3 2 1sw v in run pgood gnd mode/sync intv cc fb t jmax = 125c, ja = 43c/w, jc = 5.5c/w exposed pad (pin 9) is gnd, must be soldered to pcb 1 2 3 4 5 6 sw sw v in v in run pgood 12 11 10 9 8 7 gnd gnd mode/sync intv cc fb nc 13 gnd top view mse package 12-lead plastic msop t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 13) is gnd, must be soldered to pcb for optimal thermal performance p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3624edd#pbf ltc3624edd#trpbf lgjf 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd#pbf ltc3624idd#trpbf lgjf 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse#pbf ltc3624emse#trpbf 3624 12-lead plastic msop C40c to 125c ltc3624imse#pbf ltc3624imse#trpbf 3624 12-lead plastic msop C40c to 125c ltc3624hmse#pbf ltc3624hmse#trpbf 3624 12-lead plastic msop C40c to 150c ltc3624edd-3.3#pbf ltc3624edd-3.3#trpbf lgrg 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd-3.3#pbf ltc3624idd-3.3#trpbf lgrg 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse-3.3#pbf ltc3624emse-3.3#trpbf 362433 12-lead plastic msop C40c to 125c ltc3624imse-3.3#pbf ltc3624imse-3.3#trpbf 362433 12-lead plastic msop C40c to 125c ltc3624hmse-3.3#pbf ltc3624hmse-3.3#trpbf 362433 12-lead plastic msop C40c to 150c ltc3624edd-5#pbf ltc3624edd-5#trpbf lgrd 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd-5#pbf ltc3624idd-5#trpbf lgrd 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse-5#pbf ltc3624emse-5#trpbf 36245 12-lead plastic msop C40c to 125c ltc3624imse-5#pbf ltc3624imse-5#trpbf 36245 12-lead plastic msop C40c to 125c ltc3624hmse-5#pbf ltc3624hmse-5#trpbf 36245 12-lead plastic msop C40c to 150c ltc3624edd-2#pbf ltc3624edd-2#trpbf lgmn 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd-2#pbf ltc3624idd-2#trpbf lgmn 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse-2#pbf ltc3624emse-2#trpbf 36242 12-lead plastic msop C40c to 125c ltc3624imse-2#pbf ltc3624imse-2#trpbf 36242 12-lead plastic msop C40c to 125c operating junction temperature range (notes 2, 5) ............................................ C 40 c to 150 c storage temperature range .................. C 65 c to 150 c http://www.linear.com/product/ltc3624#orderinfo ltc3624/LTC3624-2 36242fd
3 for more information www.linear.com/ltc3624 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c. (note 2) v in = 12v, unless otherwise noted. symbol parameter conditions min typ max units v in operating voltage 2.7 17 v v out output voltage range 0.6 v in v i vin input quiescent current shutdown mode, v run = 0v burst mode operation forced continuous mode (note 3) 0.1 3.5 1.8 1.0 7 a a ma v fb regulated feedback voltage (note 4) l 0.594 0.591 0.6 0.6 0.606 0.609 v v v out regulated fixed output voltage ltc3624-3.3/LTC3624-23.3 (note 4) l 3.267 3.250 3.3 3.3 3.333 3.350 v v lt c3624-5/LTC3624-25 (note 4) l 4.950 4.925 5.0 5.0 5.050 5.075 v v v line(reg) reference voltage line regulation v in = 2.7v to 17v (note 4) 0.01 0.015 %/v v load(reg) output voltage load regulation (note 4) 0.1 % i lsw nmos switch leakage pmos switch leakage 0.1 0.1 1 1 a a r ds(on) nmos on-resistance 115 m pmos on-resistance v in = 5v 200 m d max maximum duty cycle v fb = 0.5v, v mode/sync = 1.5v l 100 % t on(min) minimum on-time 60 ns v run run input high run input low 0.35 1.0 v v i run run input current v run = 12v 0 100 na lead free finish tape and reel part marking* package description temperature range ltc3624hmse-2#pbf ltc3624hmse-2#trpbf 36242 12-lead plastic msop C40c to 150c ltc3624edd-23.3#pbf ltc3624edd-23.3#trpbf lgrh 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd-23.3#pbf ltc3624idd-23.3#trpbf lgrh 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse-23.3#pbf ltc3624emse-23.3#trpbf 362423 12-lead plastic msop C40c to 125c ltc3624imse-23.3#pbf ltc3624imse-23.3#trpbf 362423 12-lead plastic msop C40c to 125c ltc3624hmse-23.3#pbf ltc3624hmse-23.3#trpbf 362423 12-lead plastic msop C40c to 150c ltc3624edd-25#pbf ltc3624edd-25#trpbf lgrf 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624idd-25#pbf ltc3624idd-25#trpbf lgrf 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc3624emse-25#pbf ltc3624emse-25#trpbf 362425 12-lead plastic msop C40c to 125c ltc3624imse-25#pbf ltc3624imse-25#trpbf 362425 12-lead plastic msop C40c to 125c ltc3624hmse-25#pbf ltc3624hmse-25#trpbf 362425 12-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. o r d er i n f or m a t ion http://www.linear.com/product/ltc3624#orderinfo ltc3624/LTC3624-2 36242fd
4 for more information www.linear.com/ltc3624 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c. (note 2) v in = 12v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3624/LTC3624-2 is tested under pulsed load conditions such that t j t a . the ltc3624e/ltc3624e-2 is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3624i/ltc3624i-2 is guaranteed over the C40c to 125c operating junction temperature range and the ltc3624h is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operation lifetime is decreased for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? ja ) note 3: the quiescent current in forced continuous mode does not include switching loss of the power fets. note 4: the ltc3624 is tested in a proprietary test mode that servos fb to the output of the error amplifier. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when overtemperature protection is active continuous operation above the specified maximum operating junction temperature may impair device reliability. the overtemperature protection level is not production tested but guaranteed by design. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v mode/sync pulse-skipping mode burst mode operation forced continuous mode v intvcc C 0.4 1.0 0.3 v intvcc C 1.2 v v v i mode/sync mode/sync input current 0 100 na t ss internal soft-start time 1 ms i lim peak current limit v in > 5v (e-, i-grade) v in > 5v (h-grade) l l 2.4 2.3 3 3.6 a a i fb fb input current 10 na i fb(vout) feedback input leakage current fixed output versions 2 10 a v uvlo v intvcc undervoltage lockout v in ramping up 2.4 2.6 2.7 v v uvlo(hys) v intvcc undervoltage lockout hysteresis 175 mv v ovlo v in overvoltage lockout rising l 18 19 20 v v ovlo(hys) v in overvoltage lockout hysteresis 500 mv f osc oscillator frequency ltc3624/ltc3624-3.3/ltc3624-5 (e-, i-grade) (h-grade) l l 0.92 0.82 0.78 1.00 1.08 1.16 mhz mhz mhz lt c3624-2/LTC3624-23.3/LTC3624-25 (e-, i-grade) (h-grade) l l 2.05 1.8 1.7 2.25 2.45 2.6 mhz mhz mhz f sync sync capture range ltc3624/ltc3624-3.3/ltc3624-5 50 150 % LTC3624-2/LTC3624-23.3/LTC3624-25 50 140 % v intvcc v intvcc ldo output voltage v in > 4v 3.2 3.6 4.0 v v pgood power good range ltc3624/LTC3624-2 7.5 11.5 % ltc3624-3.3/ltc3624-5/LTC3624-23.3/ LTC3624-25 7.5 13 % r pgood power good resistance 280 350 t pgood pgood delay pgood low to high pgood high to low 0 32 cycles cycles ltc3624/LTC3624-2 36242fd
5 for more information www.linear.com/ltc3624 typical p er f or m ance c harac t eris t ics burst mode operation pulse-skipping mode operation load transient response soft-start operation efficiency vs load current in burst mode operation at 2.25mhz i q vs v in i q vs temperature efficiency vs load current at 1mhz efficiency vs load current in dropout t j = 25c, unless otherwise noted. load current (a) efficiency (%) 36242 g01 100 80 70 90 60 50 30 20 10 40 0 0.0001 0.1 1 2 0.01 0.001 v out = 5v v out = 3.3v v out = 2.5v v in = 12v burst mode operation load current (a) efficiency (%) 36242 g03 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 1 2 0.1 0.01 burst mode operation v in = 5v 100% duty cycle freq = 1mhz force continuous mode v in (v) 0 i q (a) 7 6 8 10 9 16 36242 g04 5 4 2 1 3 0 2 4 6 8 10 12 14 18 20 sleep shutdown temperature (c) ?50 i q (a) 6 10 8 12 100 150 36242 g05 4 2 0 0 50 shutdown sleep v in = 12v v out = 2.5v burst mode operation i out = 30ma l = 2.2h 4s/div sw 5v/div 36242 g06 v out ac-coupled 50mv/div i l 1a/div v in = 12v v out = 2.5v pulse-skipping mode i out = 10ma l = 2.2h sw 5v/div 36242 g07 v out ac-coupled 50mv/div i l 1a/div 4s/div v in = 12v v out = 2.5v i load = 0a to 1.8a forced continuous mode v out 200mv/div 36242 g08 i load 2a/div i l 2a/div 40s/div v in = 12v v out = 2.5v i load = 1a run 10v/div 36242 g09 i l 0.5a/div pgood 5v/div v out 1v/div 1ms/div load current (a) efficiency (%) 36242 g02 100 80 70 90 60 50 30 20 10 40 0 0.001 1 2 0.1 0.01 v out = 5v v out = 3v v out = 2.5v v in = 12v burst mode operation ltc3624/LTC3624-2 36242fd
6 for more information www.linear.com/ltc3624 typical p er f or m ance c harac t eris t ics efficiency vs input voltage oscillator frequency vs temperature r ds(on) vs temperature load regulation line regulation v in vs peak current limit oscillator frequency vs supply voltage reference voltage vs temperature r ds(on) vs input voltage t j = 25c, unless otherwise noted. supply voltage (v) 2 oscillator frequency (mhz) 1.0 1.5 36242 g12 0.5 0 7 12 17 2.0 v in (v) 0 r ds(on) (m) 200 400 600 100 300 500 8 10 12 36242 g14 42 6 14 16 bottom fet top fet load current (a) 0 ?0.80 ?0.20 ?0.40 ?0.60 v out (%) 0.20 0.80 1.5 36242 g16 0 0.60 0.40 0.5 1 2 forced continuous mode v in (v) 2 ?0.80 ?0.20 ?0.40 ?0.60 ?v out (%) 0.20 0.80 1412 36242 g17 0 0.60 0.40 4 6 108 16 v in (v) 0 efficiency (%) 60 80 100 15 36242 g10 40 20 50 70 90 30 10 0 5 10 20 i load = 10ma i load = 1a v out = 5v freq = 1mhz burst mode operation low dropout operation temperature (c) ?50 reference voltage 599.5 600.0 600.5 36242 g13 599.0 598.5 0 50 100 150 598.0 597.5 temperature (c) ?50 0 100 r ds(on) (m) 300 600 0 50 75 100 36242 g15 200 500 400 ?25 25 150125 bottom fet top fet v in = 12v v in (v) 0 0 peak current limit (a) 2 3 5 36242 g18 1 2 4 6 14 16 18 12 20 8 10 4 150c 25c temperature (c) ?50 oscillator frequency (mhz) 1.5 2.0 25 75 36242 g11 1.0 ?25 0 50 100 150125 0.5 0 ltc3624/LTC3624-2 36242fd
7 for more information www.linear.com/ltc3624 p in func t ions sw (pin 1/pins 1, 2): switch node connection to the inductor of the step-down regulator. v in (pin 2/pins 3, 4): input voltage of the step-down regulator. run (pin 3/pin 5): logic controlled run input. do not leave this pin floating. logic high activates the step-down regulator. pgood (pin 4/pin 6): v out within regulation indicator. fb (pin 5/pin 8): feedback input to the error amplifier of the step-down regulator. connect a resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to v in by: v out = 0.6v ? [1 + (r2/r1)] see figure 1. for fixed v out options, connect the fb pin directly to v out . intv cc (pin 6/pin 9): low dropout regulator. bypass with at least 2.2f to ground. mode/sync (pin 7/pin 10): burst mode select and ex - ternal clock synchronization of the step-down regulator. tie mode/sync to int v cc for burst mode operation with a 800ma peak current clamp, tie mode/sync to gnd for pulse skipping operation, and tie mode/sync to a volt - age between 1v and v intvcc C 1.2v for forced continuous mode. furthermore, connecting mode/sync to an external clock will sync the system clock to the external clock and put the part in forced continuous mode. gnd (pin 8, exposed pad pin 9/pins 11, 12, exposed pad pin 13) : power and signal ground. the exposed pad must be soldered to pcb ground for electrical and rated thermal performance. nc (pin 7, msop only): no connect. there is no electrical connection to this pin inside the package. (dfn/msop) ltc3624/LTC3624-2 36242fd
8 for more information www.linear.com/ltc3624 b lock diagra m ? + ? + ? + + v error amplifier ith burst amplifier main i-comparator ? + ? + overcurrent comparator reverse current comparator 0.6v fb mode/sync fixed v out run pgood intv cc clk v in ? 5v sw gnd 36242 bd v in intv cc oscillator ldo buck logic and gate drive slope compensation 1ms soft-start ltc3624/LTC3624-2 36242fd
9 for more information www.linear.com/ltc3624 o pera t ion the ltc3624 / ltc3624 -2 uses a constant-frequency, peak current mode architecture. it operates through a wide v in range and regulates with ultralow quiescent current. the operation frequency is set at either 1mhz or 2.25mhz and can be synchronized to an external oscillator 40% of the inherent frequency. to suit a variety of applications, the selectable mode/sync pin allows the user to trade off output ripple for efficiency. the output voltage is set by an external divider returned to the fb pin. an error amplifier compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. overvoltage and un - dervoltage comparators will pull the pgood output low if the output voltage is not within 7.5% of the programmed value. the pgood output will go low 32 clock cycles after falling out of regulation and will go high immediately after achieving regulation. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle. the inductor current is allowed to ramp up to a peak level. once that level is reached, the top power switch is turned off and the bottom switch (n-channel mosfet) is turned on until the next clock cycle. the peak current level is con - trolled by the internally compensated ith voltage, which is the output of the error amplifier. this amplifier compares the fb voltage to the 0.6v internal reference. when the load current increases, the fb voltage decreases slightly below the reference, which causes the error amplifier to increase the ith voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low current operation two discontinuous-conduction modes (dcms) are available to control the operation of the ltc3624/LTC3624-2 at low currents. both modes, burst mode operation and pulse- skipping, automatically switch from continuous operation to the selected mode when the load current is low. to optimize efficiency, burst mode operation can be selected by tying the mode/sync pin to intv cc . in burst mode operation, the peak inductor current is set to be at least 800ma, even if the output of the error amplifier demands less. thus, when the switcher is on at relatively light output loads, fb voltage will rise and cause the ith voltage to drop. once the ith voltage goes below 0.2v, the switcher goes into its sleep mode with both power switches off. the switcher remains in this sleep state until the external load pulls the output voltage below its regulation point. during sleep mode, the part draws an ultralow 3.5a of quiescent current from v in . to minimize v out ripple, pulse-skipping mode can be se - lected by grounding the mode/sync pin. in the ltc3624/ lt c3624 -2, pulse-skipping mode is implemented similarly to burst mode operation with the peak inductor current set to be at least 132ma. this results in lower ripple than in burst mode operation with the trade-off being slightly lower efficiency. forced continuous mode operation aside from the two discontinuous-conduction modes, the ltc3624/LTC3624-2 also has the ability to operate in the forced continuous mode by setting the mode/sync volt - age between 1v and v intvcc C 1.2v . in forced continuous mode, the switcher will switch cycle by cycle regardless of what the output load current is. if forced continuous mode is selected, the minimum peak current is set to be C266ma in order to ensure that the part can operate continuously at zero output load. high duty cycle/dropout operation when the input supply voltage decreases towards the output voltage, the duty cycle increases and slope com - pensation is required to maintain the fixed switching frequency. the ltc3624/ltc3624 -2 has internal circuitry to accurately maintain the peak current limit (i lim ) of 3a even at high duty cycles. as the duty cycle approaches 100%, the ltc3624/ LTC3624-2 enters dropout operation. during dropout, if force continuous mode is selected, the top pmos switch is turned on continuously, and all active circuitry is kept ltc3624/LTC3624-2 36242fd
10 for more information www.linear.com/ltc3624 o pera t ion alive. however, if burst mode operation or pulse-skipping mode is selected, the part will transition in and out of sleep mode depending on the output load current. this significantly reduces the quiescent current, thus prolong - ing the use of the input supply. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltc3624/LTC3624-2 constantly monitors the v in pin for an overvoltage condi - tion. when v in rises above 19v, the regulator suspends operation by shutting off both power mosfets. once v in drops below 18.5v, the regulator immediately resumes normal operation. the regulator executes its soft-start function when exiting an overvoltage condition. minimum on-time the minimum on-time is the smallest duration of the time the top power switch is allowed to be in its on state. this time is typically 60ns . in forced continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of 6% for the ltc3624 (f sw = 1mhz) and 13.5% for the LTC3624-2 (f sw = 2.25mhz ). in the rare cases that this minimum on-time is violated, the output voltage may lose regulation. in such situation, the user must choose either burst mode or pulse-skipping mode operation, or apply a slower external clock to force a slower switching frequency in order to adhere to the minimum on-time limitation. low supply operation the ltc3624 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below 2.7v . as the input voltage rises slightly above the undervoltage threshold, the switcher will begin its basic operation. however, the r ds(on) of the top and bottom switch will be slightly higher than that specified in the electrical characteristics due to lack of gate drive. refer to graph of r ds(on) versus v in for more details. soft-start the ltc3624/ltc3624 -2 has an internal 1ms soft-start ramp. during start-up soft-start operation, the switcher will operate in pulse-skipping mode. a pplica t ions i n f or m a t ion output voltage programming the output voltage is set by external resistive divider ac - cording to the following equation for adjustable output versions : v out = 0.6v ? 1+ r2 r1 ? ? ? ? the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. for fixed v out options, connect fb pin directly to v out . input capacitor (c in ) selection the input capacitance, c in , is needed to filter the square wave current at the drain of the top power mosfet. to figure 1. setting the output voltage (adjustable version) figure 2. setting the output voltage (fixed v out option) v out r2 r1 36242 f01 c ff ltc3624 sgnd fb v out 36242 f02 ltc3624 (fixed v out ) sgnd fb ltc3624/LTC3624-2 36242fd
11 for more information www.linear.com/ltc3624 a pplica t ions i n f or m a t ion special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors are very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage char - acteristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low , the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. the output droop, v droop , is prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms ? i out(max) v out v in v in v out C 1 this formula has a maximum at v in = 2v out , where: i rms ? i out 2 this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. output capacitor (c out ) selection the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, ?v out , is determined by: ?v out < ?i l 1 8 ? f ? c out +esr ? ? ? ? the output ripple is highest at maximum input voltage since ?i l increases with input voltage. multiple capaci- tors placed in parallel may be needed to meet the esr and rms current handling requirements. dr y tantalum, ltc3624/LTC3624-2 36242fd
12 for more information www.linear.com/ltc3624 a pplica t ions i n f or m a t ion usually about three times the linear drop of the first cycle. thus, a good place to start with the output capacitor value is approximately: c out = 3 i out f ? v droop more capacitance may be required depending on the duty cycle and load-step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. place this input capacitor as close to the v in pin as possible. output power good when the ltc3624/LTC3624-2s output voltage is within the 7.5% window of the regulation point, the output voltage is good and the pgood pin is pulled high with an external resistor. otherwise, an internal open-drain pull-down device (280 ) will pull the pgood pin low. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3624 / LTC3624-2 s pgood falling edge includes a blanking delay of approximately 32 switching cycles. frequency sync capability the ltc3624/ltc3624 -2 has the capability to sync to a 40% range of the internal programmed frequency. it takes 2 to 3 cycles of external clock to engage the sync mode, and roughly 2s of no clocks for the part to realize that the sync signal is gone. once engaged in sync, the ltc3624/LTC3624-2 immediately runs at the external clock frequency. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ?i l = v out f ? l 1? v out v in(max) ? ? ? ? lower ripple current reduces power losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . to guarantee that ripple current does not exceed a specified maximum, the induc - tance should be chosen according to: l = v out f ? ?i l(max) 1? v out v in(max) ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as the inductance or frequency in - creases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have ver y low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard , which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from toko, vishay, coilcraft, nec/tokin, cooper, tdk and wrth elektronik. refer to table 1 for more details. ltc3624/LTC3624-2 36242fd
13 for more information www.linear.com/ltc3624 a pplica t ions i n f or m a t ion checking transient response the regular loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to the ?i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feedforward capacitor can be added to improve the high frequency response, as table 1. inductor selection table inductor inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) manufacturer xal4020 series 1.0 1.5 2.2 13.25 21.45 35.20 8.7 7.1 5.6 4.3 4.3 4.3 4.3 4.3 4.3 2.1 2.1 2.1 coilcraft www .coilcraft.com xa l4030 series 3.3 4.7 6.8 26.0 40.1 67.4 5.5 4.5 3.6 4.3 4.3 4.3 4.3 4.3 4.3 3.1 3.1 3.1 ihlp-1616bz-11 series 1.0 2.2 24 61 4.5 3.25 4.3 4.7 4.3 4.7 2 2 vishay www .vishay.com ihlp-2020bz-01 series 1 2.2 3.3 4.7 5.6 6.8 18.9 45.6 79.2 108 113 139 7 4.2 3.3 2.8 2.5 2.4 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 2 2 2 2 2 2 fd v0620 series 1 2.2 3.3 4.7 18 37 51 68 5.7 4 3.2 2.8 6.7 7.4 6.7 7.4 6.7 7.4 6.7 7.4 2 2 2 2 toko www .toko.com mp lc0525l series 1 1.5 2.2 16 24 40 6.4 5.2 4.1 6.2 5.4 6.2 5.4 6.2 5.4 2.5 2.5 2.5 nec/tokin www .nec-tokin.com hc p0703 series 1 1.5 2.2 3.3 4.7 6.8 8.2 9 14 18 28 37 54 64 11 9 8 6 5.5 4.5 4 7 7.3 7 7.3 7 7.3 7 7.3 7 7.3 7 7.3 7 7.3 3 3 3 3 3 3 3 cooper bussmann www .cooperbussmann.com r lf7030 series 1 1.5 2.2 3.3 4.7 6.8 8.8 9.6 12 20 31 45 6.4 6.1 5.4 4.1 3.4 2.8 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 3.2 3.2 3.2 3.2 3.2 3.2 tdk www .tdk.com we-tpc 4828 series 1.2 1.8 2.2 2.7 3.3 17 20 23 27 30 3.1 2.7 2.5 2.35 2.15 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 2.8 2.8 2.8 2.8 2.8 wrth elektronik www .we-online.com ltc3624/LTC3624-2 36242fd
14 for more information www.linear.com/ltc3624 a pplica t ions i n f or m a t ion shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r2 , which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharge input capacitors are effectively put in paral - lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap ? controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft-starting. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a per cent - age of input power. although all dissipative elements in the cir cuit produce losses, three main sour ces usually account for most of the losses in ltc3624/LTC3624-2 circuits: 1) i 2 r losses, 2) switching and biasing losses, 3) other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the switching current is the sum of the mosfet driver and control currents. the power mosfet driver current results from switching the gate capacitance of the power mosfets. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from in to ground. the resulting dq/dt is a cur - rent out of in that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. the power loss is thus: switching loss = i gatechg ? v in the gate charge loss is proportional to v in and f and thus their effects will be more pronounced at higher supply voltages and higher frequencies. 3. other hidden losses such as transition loss and cop - per trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is very important to include these system level losses in the design of a system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the ltc3624/ ltc3624 -2 internal power devices switch quickly enough that these losses are not significant compared to other sources. these losses plus other losses, including diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss. thermal conditions in a majority of applications, the ltc3624/LTC3624-2 does not dissipate much heat due to its high efficiency and low thermal resistance of its exposed pad dfn package. however, in applications where the ltc3624/LTC3624-2 is running at high ambient temperature, high v in , high switching frequency, and maximum output current load, ltc3624/LTC3624-2 36242fd
15 for more information www.linear.com/ltc3624 the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 160c , both power switches will be turned off until the temperature drops about 15c cooler. to avoid the ltc3624/ltc3624 -2 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera - ture rise is given by: t rise = p d ? ja as an example, consider the case when the ltc3624/ ltc3624 -2 is used in applications where v in = 12v , i out = 2a , f = 1mhz , v out = 1.8v . the equivalent power mosfet resistance r sw is: r sw =r ds(on)top ? v out v in + ? r ds( no )bot ? 1 v out v in ? ? ? ? ? ? = 200m ? 1.8v 12v +100m ? 1? 1.8v 12v ? ? = 115m the v in current during 1mhz force continuous operation with no load is about 8ma, which includes switching and internal biasing current loss, transition loss, inductor core loss and other losses in the application. therefore, the total power dissipated by the part is: p d = i out 2 ? r sw + v in ? i in(q) = 2a 2 ? 115m + 12v ? 8ma = 556mw the dfn 3mm 3mm package junction-to-ambient thermal resistance, ja , is around 43c /w. therefore, the junction temperature of the regulator operating in a 25c ambient temperature is approximately: t j = t a + t rise = 25c + 0.556w ? 43c/w = 49c remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation assuming that r sw increased 5% at 49c yields a new junction temperature of 50c. if the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or forced air flow. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3624/ltc3624 -2 (refer to figure 3). check the following in your layout: 1. do the capacitors c in connect to the v in and gnd as close as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. 2. are c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line ter - minated near gnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace length should be minimized. keep r1 and r2 close to the ic. 4. solder the exposed pad (pin 9) on the bottom of the package to the gnd plane. connect this gnd plane to other layers with thermal vias to help dissipate heat from the ltc3624/LTC3624-2. 5. keep sensitive components away from the sw pin. the input capacitor, c in , feedback resistors, and intv cc bypass capacitors should be routed away from the sw trace and the inductor. 6. a ground plane is preferred. 7. flood all unused areas on all layers with copper, which reduces the temperature rise of power components. these copper areas should be connected to gnd. a pplica t ions i n f or m a t ion ltc3624/LTC3624-2 36242fd
16 for more information www.linear.com/ltc3624 design example as a design example, consider using the ltc3624/ LTC3624-2 in an application with the following specifications: v in = 10.8v to 13.2v v out = 3.3v i out(max) = 2a i out(min) = 0a f sw = 2.25mhz because efficiency and quiescent current are important at both 500ma and 0a current states, burst mode operation will be utilized. given the internal oscillator of 2.25mhz , we can calcu - late the inductor value for about 40% ripple current at maximum v in : l = 3.3v 2.25mhz ? 0.8a ? ? ? ? 1? 3.3v 13.2v ? ? ? ? = 1.38h given this, a 1.5h inductor would suffice. c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, a 47f ceramic capacitor will be used. c in should be sized for a maximum current rating of: i rms = 2a 3.3v 13.2v ? ? ? ? ? 13.2v 3.3v ? 1 ? ? ? 1/2 = 0.86a bypassing the v in pin to ground with 10f ceramic capaci - tors is adequate for most applications. a pplica t ions i n f or m a t ion figure 3a. sample pcb layout-top side figure 3b. sample pcb layout-bottom side top layer gnd gnd 36242 f03a gnd c in c in v in v out c out c_intvcc l1 ltc3624 bottom layer gnd 36242 f03b gnd gnd c in v in v out c out (opt) c out (opt) ltc3624/LTC3624-2 36242fd
17 for more information www.linear.com/ltc3624 p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) please refer to http://www.linear.com/product/ltc3624#packaging for the most recent package drawings. ltc3624/LTC3624-2 36242fd
18 for more information www.linear.com/ltc3624 p ackage descrip t ion msop (mse12) 0213 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev g) please refer to http://www.linear.com/product/ltc3624#packaging for the most recent package drawings. ltc3624/LTC3624-2 36242fd
19 for more information www.linear.com/ltc3624 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 04/14 added fixed output options. clarified ordering information. clarified electrical specifications. clarified pin functions. 1 2 3, 4 7 b 08/14 clarified typical application clarified pin functions clarified v fb and v out in electrical specifications clarified note 4 clarified applications information and figure 1 figure 2 is now figure 3 bottom typical application clarified 1 2 3 4 10 14, 15 18 c 06/15 added msop package options and h-grade options added h-grade electrical parameters and 150c to note 2 updated i q vs temperature graph to 150c updated oscillator frequency and v ref graphs vs temperature to 150?c updated pin functions for msop package versions added msop package description and drawing 2, 3 4 5 6 7 18 d 04/16 corrected a typographical error 1 ltc3624/LTC3624-2 36242fd
20 for more information www.linear.com/ltc3624 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2014 lt 0416 rev d ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3624 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3621 17v, 1a, 2.25mhz/1mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 3.5a, i sd < 1a, 2mm 3mm dfn-6, msop-8e packages lt c3600 15v, 1.5a, 4mhz synchronous rail-to-rail single resistor step-down regulator 95% efficiency , v in : 4v to 15v, v out(min) = 0v, i q = 700a, i sd < 1a, 3mm 3mm dfn-12, msop-12e packages lt c3601 15v, 1.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency , v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 14a, 3mm 3mm qfn-16, msop-16e packages lt c3603 15v, 2.5a (i out ) 3mhz synchronous step-down dc/dc converter 95% efficiency , v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, msop-16e packages lt c3633/ltc3633a 15v/20v, dual 3a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency , v in : 3.6v to 15v/20v, v out(min) = 0.6v, i q = 500a, i sd < 15a, 4mm 5mm qfn-28, tssop-28e packages ltc3605/ltc3605a 15v/20v, 5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 15v/20v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 package lt c3604 15v, 2.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency , v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 14a, 3mm 3mm qfn-16, msop-16e packages 4.2v out , 1mhz, burst mode operation 1.2v out , synced to 500khz, forced continuous mode 12v step-down with 2a output current limit, 2.25mhz 32.4k 15pf 2.2f c out 47f 36242 ta04 l1 1.5h l1: coilcraft xal4020-152me v out 12v 619k v in run sw v in 13v to 17v LTC3624-2 gnd fb mode/sync intv cc c in 10f 100k 22pf 2.2f c out 47f 36242 ta02 l1 2.2h l1: coilcraft xal4020 -222me v out 4.2v 2a max 604k v in run sw v in 5v to 17v ltc3624 gnd fb mode/sync intv cc c in 10f 22pf 2.2f c out 47f 36242 ta03 l1 2.2h 604k 500khz clk v in run sw ltc3624 gnd fb mode/sync intv cc c in 10f v in 2.7v to 17v v out 1.2v 2a max 604k l1: coilcraft xal4020 -222me ltc3624/LTC3624-2 36242fd

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